| 摘要 |
PURPOSE:To extract a regenerative clock with less shift from a PLL with a simple constitution, by adding an RF level detecting circuit and the like to the titled circuit so as to make an input signal to the PLL zero or small even if a part of transmitted time series digital signal is missing. CONSTITUTION:An RF digital signal from a regenerative digital input terminal 7 is demodulated at a demodulating circuit 8, applied to an edge detecting circuit comprising an exclusive OR circuit 12 and a delay circuit 13 via an LPF 10 for detecting edge parts respectively. A frequency being a natural number multiple of its edge detecting signal is extracted at a capacitor C1 and a film L1 for tank circuit and applied to the PLL17 via an amplifier 14 and the like. Further, a signal from a terminal 7 is applied to the RF level detecting circuit 9 to detect the signal level for discriminating the consecution time below a prescribed level not demodulated at the circuit 8 normally at a time discriminating circuit 15. Further, an output of the circuit 15 is applied to a variable impedance element 16 to decrease an input impedance of the PLL17, allowing to extract a prescribed clock signal frequency from the PLL17. |
