摘要 |
<p>The device (300) has an offset switching stage (32) cascaded in downstream with a switching stage (31), where the stage (32) has high and low switching units (303`, 304`) respectively for switching an output signal. High and low inverters (301`, 302`) respectively act on the switching units via upstream high and upstream low control points (E, F), where high and low inverters (301, 302) of the stage (31) act on high and low switching units (303, 304) of the stage (31). A generation unit of the control points is time-staggered with respect to high and low memory points (C, D).</p> |