发明名称 PROCESS CONTROLLER
摘要 PURPOSE:To reduce the frequency of data transmission and a load, to eliminate the need for the intervention of operators in case of a shutdown of a host device (computer), and to obtain a device which is controllable in an optimum state by providing a subordinate device with a memory for storing data on the host device and performing process control. CONSTITUTION:The subordinate device is provided with a timer and the memory for storing the data on the host device and the process control is performed on the basis of the memory contents and a timer signal. For example, the host device 10 outputs command value data, etc., found on the basis of the current process value to the subordinate device 30 through a transmission part 20 together with a timer reset signal. Then, data on the command value, etc., inputted from the host device 10 is stored in the memory 32 and the timer 31 is reset by the timer reset signal to clock time. An arithmetic control part 33 performs arithmetic for finding the command value, etc., on the basis of the output signals of the memory 32 and timer 31 and the command value, etc., is used to sent out an operation signal for the process control.
申请公布号 JPS58184603(A) 申请公布日期 1983.10.28
申请号 JP19820067935 申请日期 1982.04.22
申请人 TOKYO SHIBAURA DENKI KK 发明人 DEMURA HIROYUKI;KOBAYASHI MITSUO
分类号 G05B9/03;G05B7/02 主分类号 G05B9/03
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