| 摘要 |
PURPOSE:To prevent the number of low order processors that can be connected from being restricted by the size of address space of high order processors by providing an FIFO memory for address information transfer, and providing an address register in each shared memory. CONSTITUTION:The system is provided with an vacant address information FIFO (First-In First-Out) memory 4 for transferring address information from a high order processor 1 respective shared memories 12, 22,...,N2, a notification FIFO memory 5 for transferring address information from low order processors 11, 21,...,N1 to the high order processor 1 and an FIFO memories. The position of the shared memories 11, 21,...,N1 on the address space of the high order processor 1 is not determined and arranged dynamically. Thus, the number of shared memories that become in use simultaneously is restricted by the maximum value of the address space of the high order processor 1. However, the number of shared memories that can be connected is not restricted. |
