| 摘要 |
PURPOSE:To make the title circuit immune from the internal noise of the circuit by providing an adder/correction circuit adding/correcting a binary quantizing signal and a binary correcting quantizing signal to output ternary state quantizing signal so as to suppress the internal operating voltage of the circuit to the same level as the input signal voltage. CONSTITUTION:The titled circuit consists of a delay device 42 retarding the 1st integration signal, a correction quantizer 46 deciding the polarity of the 1st integration signal a binary quantized correction signal OS 12 and the adder/ correction circuit applying addition/correction to a binary quantized signal OS 11 and the correction quantized signal OS 12 to generate a ternary-state quantized signal OS 1 and outputting the said signal as a digital output signal OS 1. Assuming the binary output of the 1st quantized signal OS 11 and the 2nd quantized signal OS 12 as (+1, -1), then the output signal OS '1' being the addition and correction of them is a ternary-state output (+1, 0, -1). Thus, the integration signal voltage of the 1st and 2nd integration signals, that is, the internal operating voltage is suppressed to the same level with respect to an analog input signal voltage, for instance.
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