| 摘要 |
<p>PURPOSE:To reduce the power consumption, by supplying clocks of a frequency matched to the operation mode of a processing circuit to the processing circuit to operate it. CONSTITUTION:When a microcomputer enters into a high-speed operation mode of the normal operation, a prescribed instruction code is set to an idle register 6. Contents of this code are decoded by a decoder 7, and a high-level signal is generated on a line 8 and is applied to an AND circuit 3. High-speed clocks obtained by dividing a frequency (f) from an oscillator 1 to f/n in a frequency divider 2 are supplied from the circuit 3 to an internal processing circuit of the computer through an OR circuit 13. When the processing in the high-speed mode is terminated and the device enters into the idle state, a corresponding instruction code is set to the register 6. Contents of this code are decoded by the decoder 7, and a high-level signal is generated on a line 9 and is applied to an AND circuit 4. The circuit 4 outputs low-speed clocks obtained by dividing the frequency (f) to f/m in the frequency divider 2, the these clocks are supplied to the processing device through the circuit 13. Since the power consumption of the processing device constituted with a CMOS is dependent upon the operating frequency, the power consumption is reduced.</p> |
