| 摘要 |
PURPOSE:To reduce the effect of reception data pattern on bit synchronism, by applying a differential two-phase code or an FM code to a data input terminal, frequency-dividing a clock signal and applying the result to a clock input terminal, in a bit synchronizing circuit of PCM communication. CONSTITUTION:A differential two-phase code or an FM code having one changing point of one bit of reception data is applied to a data input terminal 1 of a bit synchronizing circuit 15 to double the period of a clock signal applied to a clock input terminal 2. An output timing signal of the circuit 15 is applied to a T type FF16 to obtain an output with 1/2 frequency-division. A timing signal 3a is almost synchronized with a reception code 1a and also a timing signal 16a output from the FF16 is almost synchronized with the reception code 1a. |
