发明名称 |
Circuit arrangement for shortening the program run of microprocessor systems |
摘要 |
A circuit arrangement for shortening the program run of microprocessors during the selection of slow random-access memories, in which the write pulse is extended with the aid of a bistable flip flop and, by using the address enable signal (ALE), a likewise extended memory selection signal (CS) is obtained. This eliminates the need for inserting a wait cycle. <IMAGE>
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申请公布号 |
DE3143806(A1) |
申请公布日期 |
1983.05.19 |
申请号 |
DE19813143806 |
申请日期 |
1981.11.04 |
申请人 |
SIEMENS AG |
发明人 |
LECHLER,WALTER,DIPL.-ING. |
分类号 |
G06F12/06;G06F13/42;(IPC1-7):G06F13/06 |
主分类号 |
G06F12/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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