| 摘要 |
PURPOSE:To operate the titled circuit with one kind of a DC power supply, by connecting in cascade a depletion junction field effect transistor (D-JFET) and an enhancement junction field effect transistor (E-JFET), and constituting an inverter of two stages. CONSTITUTION:When an input voltage VIN is at L level and a signal of 0V, even if a voltage VG5 is at L level, the drain voltage becomes a positive voltage VG5L with a D-JFETQ51. VG5L=IDSXRDS is obtained when the voltage VG2 between the gate and source of the D-JFETQ51 is reduced to zero, where ISD is a source-to-drain current, and RDS is a resistance between the source and drain, taking into consideration the values of IDS and RDS normally, the VG5L can be made to <=0.5V sufficiently. In setting a threshold voltage Vth of the E-JFETQ52 to a suitable value between 0.1-1V, the E-JFETQ52 is turned off at the L level VG5L. Thus, the inverter at the post stage using the Q52 can function as a normally-off type. |
