| 摘要 |
<p>A logic gate circuit utilizing the Josephson effect is disclosed which has very short gate delay time and wide operational margins and is feasible for a high degree of integration. The circuit comprises a group of N (N >/= 2) of parallel branches, each branch consisting of a series connection of resistor (R11, R12, R13) and a Josephson junction (J11, J12, J13), connected in parallel, a chain of series connected N-1 resistors (R21, R22) each connecting the junction points of resistor and Josephson junction of two adjacent branches, and a further Josephson junction (J3) connecting an input terminal with one end of said chain of resistors. Each resistor and each Josephson junction has a predetermined resistance and critical current, respectively.</p> |
