发明名称 TEST SYSTEM FOR OPERATION COLLATION OF DUAL TIME DIVISION CHANNEL
摘要 PURPOSE:To operate a collating circuit only for the occurrence of a true trouble to eliminate the ineffective processing of a central processing unit, by synchronizing dual channel systems and controlling parts with each other, respectively. CONSTITUTION:Control instruction receiving circuits 6 and 7 of channel systems 2 and 3, which are made dual in the thermal stand-by type, and a control instruction transmitting circuit 8 of a channel controlling part 1 receive clocks from a clock supply device 4 through lines 11-13 to operate. When the control instruction transmitting circuit 8 transmits a channel controlling instruction to channel systems through lines 9 and 10, this instruction reaches channel systems 2 and 3 in different times by the difference between transmission delays on lines 9 and 10. Channel systems 2 and 3 take in the control instruction at the same time prescribed by the clock by receiving circuits 6 and 7 and start the control operation. Therefore, operations of channel systems 2 and 3 coincide with each other in respect to time, and a collating circuit 5 detects the dissidence only when operations of channel systems do not coincide with each other truly.
申请公布号 JPS5825750(A) 申请公布日期 1983.02.16
申请号 JP19810123828 申请日期 1981.08.07
申请人 FUJITSU KK;NIPPON DENSHIN DENWA KOSHA;NIPPON DENKI KK;HITACHI SEISAKUSHO KK;OKI DENKI KOGYO KK 发明人 MURAKAMI KOUZOU;SANBE TAKESHI;KAWADA AKIRA;GOUHARA SHINOBU;AKATA KAZUHIKO
分类号 H04M3/26;H04M3/24;H04Q3/52;H04Q11/04 主分类号 H04M3/26
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