| 发明名称 |
Logic state analyzer |
| 摘要 |
A logic state analyzer stores into a data acquisition memory only state data meeting preselected qualification state criteria chosen to weed out state data not of interest among the totality of states occuring within a collection of digital signals. The data acquisition memory retains only the last m-many states stored therein. A selectable integer k, o</=k</=m, determines how many additional storage operations are performed for qualified state data following the detection of a preselected trigger condition. The actual number of states occurring in the collection of digital signals after the trigger condition but before the storage of the kth qualified data state can be many times the value of k. Qualifying the state data prior to storage allows a modest size data acquisition memory to do the work of a much larger memory and spares the user the task of sorting through much state data known not to be of interest. The preselected qualification criteria may include don't-cares in the definition of the qualification state, as well as the logical OR'ing of a plurality of such qualification states.
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| 申请公布号 |
US4373193(A) |
申请公布日期 |
1983.02.08 |
| 申请号 |
US19800210462 |
申请日期 |
1980.11.25 |
| 申请人 |
HEWLETT-PACKARD COMPANY |
发明人 |
HAAG, GEORGE A.;FOGG, O. DOUGLAS;GREENLEY, GORDON A.;SHEPARD, STEVE A.;TERRY, F. DUNCAN |
| 分类号 |
G06F11/25;G06F17/40;(IPC1-7):G06F3/05;G06F3/15 |
主分类号 |
G06F11/25 |
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