发明名称 DUTY CONTROLLING CIRCUIT
摘要 PURPOSE:To reduce the duty change of an output pulse as compared with the duty change of an input pulse, by applying a signal obtained by giving the inversion and delay to the input pulse to said input pulse. CONSTITUTION:The input pulse of an input terminal INPUT is inverted through a gate X1 to be applied to a resistance R1 and at the same time delayed by a delaying circuit DL and a gate X2 to be fed to a resistance R2. A pulse of about 50% duty emerges as a point C of connection between the resistances R1 and R2 when the duty of the input pulse is 7:5 and the resistance R1 is nearly equal to the resistance R2. This pulse is delivered through an output terminal OUT and via a gate X3.
申请公布号 JPS583421(A) 申请公布日期 1983.01.10
申请号 JP19810101903 申请日期 1981.06.30
申请人 FUJITSU KK 发明人 KUBOTA KATSUHISA
分类号 H03K5/04;H03K5/06 主分类号 H03K5/04
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