发明名称 DIGITAL INPUT LIMITING CIRCUIT
摘要 PURPOSE:To achieve smooth ascent and descent in a prescribed route, when a reference signal is changed, by providing an interval comparator which outputs an interval difference signal corresponding to the difference of pulse intervals and a frequency changing rate adjuster. CONSTITUTION:An interval comparator outputting an interval difference signal corresponding to the differece of pulse intervals, a frequency changing rate adjuster outputting a rate of change signal, and a pulse interval operator generating a digital signal with pulse interval operated based on the interval difference signal and the rate of change signal are provided for a titled circuit. For example, a reference signal f0 is inputted to a pulse inteval comparator 1, which sequentially compares a pulse inteval T0 of the reference signal f0 and pulse intervals T1-Tn in frequency f1 of a signal before the input of this reference signal to output a deviation signal Td that is inputted to a pulse operator 2. A pulse signal f2 is generated based on the deviation signal Td and a rate reference signal R from a DELTAf adjuster 3 and the signal f2 is inputted to the comparator 1 via a pulse interval memory 4.
申请公布号 JPS57193801(A) 申请公布日期 1982.11.29
申请号 JP19810077517 申请日期 1981.05.22
申请人 TOKYO SHIBAURA DENKI KK 发明人 SHIMIZU TERUYOSHI
分类号 G05B7/02;G05B5/01 主分类号 G05B7/02
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