发明名称 |
Continuously adjustable delay-locked loop |
摘要 |
A circuit and method are shown for a continuously adjustable delay circuit. The present invention utilizes two signal delay paths controlled by a tuning signal wherein each delay path receives a reference signal. The first delay path delays the reference signal in response to the tuning signal in a manner that is complementary to the manner in which the second delay path delays the reference signal in response to the tuning signal. By selecting one of the signal output by the first delay path and the signal output by the second delay path and switching between the two signals at a point when the two signals are separated by a period of the reference signal, a delay of the reference signal can be continuously adjusted.
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申请公布号 |
US6008680(A) |
申请公布日期 |
1999.12.28 |
申请号 |
US19970919248 |
申请日期 |
1997.08.27 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
KYLES, IAN;PATENAUDE, JEAN-MARC |
分类号 |
H03K5/13;H03L7/08;H03L7/081;H03L7/087;H03L7/089;H04L7/033;(IPC1-7):H03K5/13 |
主分类号 |
H03K5/13 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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