| 摘要 |
PURPOSE:To reduce the peak load of a bus, by monitoring the bus load through an input/output device and varying the using frequency of the bus in accordance with the bus load. CONSTITUTION:The data to be fed to a CPU1 from an input/output device 3 is prepared at a buffer memory 11. A DMA control circuit DMAC9 delivers a bus occupying request REQ2-3 to a bus occupancy control circuit BA4 and a DMA control circuit 1-2. The circuit BA4 sends back ACK2-4 in case when the bus 2 is not in use. Then the circuit DMAC9 reads the data by which the address of a counter 10 is transferred to an address bus 2-1 out of the memory 11 via a control circuit MCONT12 and then delivers it to a data bus 2-2. Thereafter, a data fetch request SRVI2-5 is delivered. The circuit 1-2 writes the data on the bus 2-2 into a memory 1-1. Then SRVO2-10 is delivered after the fetching of data is over. |
