| 摘要 |
Data is transmitted or received by a master processing unit (12) through a data channel (16) which is coupled to a slave processing unit (not shown). All data interchanges occur on a bit by bit serial basis, with the interchange of each bit of information being initiated by a clock pulse emitted from a clock pulse generator (28) under the control of the master control (34). Information bits are transmitted by the master unit (12) only in conjunction with such clock pulses, and information bits are received by the slave processing unit only upon receipt of clock pulses transmitted through the data channel (16). Transmission by the slave unit and reception by the master unit (12) through data channel (16) are similarly controlled by the clock pulses. Short data pulses signify binary zeros, and longer data pulses signify binary ones. |
