| 摘要 |
PURPOSE:To improve the response to failures, by providing a shift register which inputs a pulse train having a period within a prescribed range as clock and a watchdog pulse as a reset signal. CONSTITUTION:If the period of a pulse train is longer than an interruption routine execution time and no failure takes place in the operation of a microcomputer, one time watchdog timer pulse is outputted in one period of pulse train. A shift register 2 is reset with this pulse to obtain a pulse output with the same period as that of the inputted pulse train for Q1 output (output of the 1st stage). A Qn output (output of the final stage) is kept at 0 and no alarm signal is outputted. On the other hand, a microcomputer 1 runs away and no watchdog timer pulse is outputted, then the Q1 output is kept at 1 and the Qn alarm output 1 is outputted at the input of the (n-1)-th or the n-th pulse from the start of runaway. |
