发明名称 DIGITAL LIMITER
摘要 PURPOSE:To increase a dynamic range by selecting a sign bit which corresponding to that of input data when the sign bits of the input data and threshold- level data are equal. CONSTITUTION:A gate 10 is provided for exclusive OR between input data and threshold-level data, and the output data of an adder 1 which adds the input data and threshould-level data mutually or the input data is selected by a selector 11 corresponding to the output of the gate 10. When the input data and threshold-level data has the same sign, the selector 11 selects and applies the sign bit of the input data to a D type FF3, where the sign bit is latched. When the input data and threshold-level data have different signs, the adder 1 never causes an overflow, so the sign bit of the output data of the adder 1 is selected by the selector 11 and applied to the D type FF3.
申请公布号 JPS5783914(A) 申请公布日期 1982.05.26
申请号 JP19800159486 申请日期 1980.11.14
申请人 HITACHI SEISAKUSHO KK 发明人 HASHIDA MITSUYOSHI
分类号 H03G3/02;H03G7/00;H03G11/00 主分类号 H03G3/02
代理机构 代理人
主权项
地址
您可能感兴趣的专利