| 摘要 |
PURPOSE:To set priority variably when requests to use a bus are issued simultaneously, by providing a switching circuit which generates a priority switching signal when a value exceeds a prescribed value. CONSTITUTION:Flip-flop FF 111 and 112 consist of a reception circuit which receives a bus request signal, and an FF 122 recognizes the simultaneous arrival of the bus request signals via an AND gate 121, and outputs a simultaneous arrival signal. Gates 131 and 132 suppress the output of a bus occupancy permission signal when another request signal has a higher priority order and the requests are issued simultaneously, and suppress the occupancy permission signal when another request occupies a bus. FFs 133 and 134 output the bus occupancy permission signal, and a switch 135 is interlocked and switched by the priority switching signal based on the priority to occupy and bus. A register 221 multiplies and adds the content of an error register 212 which stores the simultaneous arrival signal by the value of a register 211 which stores the value of weight transmitted from a CPU, and outputs an added result carry signal as the priority switching signal. |
