发明名称 PLL FREQUENCY SYNTHESIZER TUNER
摘要 PURPOSE:To perform stable channel selecting operation by changing frequency dividing ratios of a prescaler by receiving N-1 count output of a program counter. CONSTITUTION:This tuner is provided with flip-flop circuit 6 that receives N-1 count detection output (a) in response to the N-value set output of program counter 4 and then regards output (phi) of prescaler 3 as a clock signal, and the frequency- dividing-ratio changeover signal of prescaler 3 is generated by its output. Program counters 4 and 5 are reset by the M count output of program counter 5 set to count value M. The output of counter 5 is compared with the frequency division output of oscillator 8 by phase comparator 7 to control local oscillating circuit 2, receiving a signal of a desired frequency.
申请公布号 JPS5691538(A) 申请公布日期 1981.07.24
申请号 JP19790168396 申请日期 1979.12.26
申请人 HITACHI LTD;HITACHI OME ELECTRONIC CO 发明人 NAKAGAWA TADASHI
分类号 H03J7/28;H03L7/193;H04B1/26 主分类号 H03J7/28
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