| 摘要 |
Increasing the speed and hit ratio for data fetches in data processing systems is essential. Increased data fetch speed normally results from using a fast cache memory with a slower main memory. The hit ratio for such fetches can be increased by using cache memory (26') which incorporates data buffer (34') that stores blocks of data that are varied in size and a set associative memory as index (32') which stores block addresses for main memory (14), which addresses are associated with the data blocks stored in buffer (34'). The block sizes are varied by selectively inhibiting address bits provided to an input (40') of the index (32') by address inhibit circuit (54) in response to information stored in block size register (54). Such block size information is also provided to a fetch generate counter (60') and a fetch return counter (62') for controlling the number of words transferred as a block from main memory (14) to cache memory (26'). |
