| 摘要 |
PURPOSE:To make it possible to execute the data input processing with high reliability, by supplying a selective signal of the counter in order from the multiplexer whose response speed is quicker, in the data processing unit which outputs the parallel input data in series. CONSTITUTION:When the counter 11 is made its initial status by a clear signal CLR, the multiplexer 13 input 8 input data one after another, and outputs the output data in series to the output terminal Q. Subsequently, when the counter 11 counts a clock pulse CLK, and the output terminals 2<3>, 2<4> become 1 and 0, a selective signal of the multiplexer 14 is output to the output terminal 1 of the decoder 12, the multiplexer 14 inputs the input data one afrer another, and each data is output in series. When the output terminals 2<3>, 2<4> of the counter 11 become 0 and 1, the multiplexer 15 is operated. Since the response speed of the multiplexers 13- 15 is made slower in order, a wrong data is never input. |
