| 摘要 |
PURPOSE:To exclude the fault occurrence detecting circuit and thus reduce the whole hard scale, by monitoring the presence or absence of the logic conflicet and the timing fault by the control circuit of each part for the transmission/reception state of the control signals which are transferred among the parts. CONSTITUTION:An integrated control is given to control units 12', 13', 14' and others through central processor 11. Then the signal conversion is carried out when the signals are transmitted and received to/from the terminal by signal reception and transmission converting parts 12 and 13 which receive the control of control circuits 12' and 13' respectively. The signals converted into the digital signals are stored at storing part 15. Furthermore, the signal transmission/reception is carried out to other signal storing devices by interdevice signal transfer part 14 which receives the control of control circuit 14'. Then a monitor is given control circuits 12', 13' and 14' to the presence or absence of the logic conflict and the timing fault for the transmission/reception state of the control signals which are transferred among those parts. Then the detection result is displayed at fault display part 16 via processor 11. |
