| 摘要 |
PURPOSE:To realize a high integration by storing one gate forming the TTL logic circuit into one land. CONSTITUTION:Both p-type regions 6 and 8 are formed on the surface of n-type region 4 to be used for the base region of transistors Q1 and Q2, and n<+>-type regions 10 and 12 are formed on the surface area to be used for the emitter regions. And deep p<+>-type region 14 is used for isolation of each land as well as the substrate contact. Then p-type region 15 is formed at the area from region 14 to region 4 to be used for the collector region of transistor Q3. The inverter shares region 4 to form each transistor and others. Thus one gate can be formed with one land and one isolation. As a result, the occupying area can be reduced greatly with every gate. |
