| 摘要 |
PURPOSE:To increase the speed for both the access time and the cycle time, by reading out the data of one block and then delivering the lower-rank bits of the address register in sequence after renewing them. CONSTITUTION:The command is given to set contents A of line 23 to address register 1 from timing control circuit 3 via line 22. As line 15 is 0 at first, the data of the even side is delivered to line 21 from memory chip 12. At this time point, line 17 is set to 1. As a result, the contents of address A is set to data register 4. Then line 15 turns to 1, and the data of the odd side is delivered to line 21. At this time point, line 16 is set to 1. Thus the data of address A+1 is set to register 5. Then either A or A+1 is selected through selector 11 and based on the result of macroorder execution, starting the next cycle. At this moment, a comparison is given between the time from 1 of line 22 to 1 of line 17 and the time from 1 of line 17 to 1 of line 16. Thus the former is large, and the latter is small each. |
