| 摘要 |
PURPOSE:To enhance the integrating degree of a memory device by forming the gate electrode of an IGFET forming an FF circuit as memory means of a first polycrystalline silicon layer, while power lines of second polycrystalline silicon layer being different from the first layer in mesh state. CONSTITUTION:A memory cell is formed of n-channel transfer gate FET elements 1, 2, n-channel FF FET elements 3, 4 and p-channel load load FET elements 5, 6. In this configuration polycrystalline silicon containing n-type impurity is used for the gate electrodes of the elements 3-6, digit lines 7, 8 are formed of aluminum and connected through openings to the diffused layers of the elements 3, 4, respectively. The gate electrodes of the elements 3, 4 are connected to the line wire 9 of the polycrytalline silicon, and the source diffused layers of the elements 5, 6 are connected to power lines 10 introduced from the respective cells. The drain diffused layers 11, 12 of the elements 5, 6, respectively are connected through aluminum wires 15, 16, respectively to the drain diffused layers 13, 14 of the elements 3, 4, respectively. |
