发明名称 PLL FREQUENCY SYNTHESIZER
摘要 PURPOSE:To avoid the step-out by deciding the height relation between the output signal frequency of the voltage control oscillator and the frequency of the 2nd input signal and then to give the control to the transmission of the beat frequency signal to the digital phase comparator. CONSTITUTION:The 1st and 2nd input signals are applied to input terminals 1 and 2. The output frequency of voltage control oscillator 4 receives the beat-down by the 2nd frequency at mixer 5 and then is sent to gate 11. While the output frequency of oscillator 4 receives a comparison of the height with the 2nd frequency through digital phase comparator 10. And in case the output frequency of oscillator 4 is higher than the 2nd frequency, gate 11 is opened for application of the beat frequency signal to comparator 8. As a result, oscillator 4 is controlled to secure the synchronism. While in case the output frequency is lower than the 2nd frequency, gate 11 closes to inhibit the input of the beat frequency to comparator 8. And the output frequency of oscillator 4 is raised higher than the 2nd frequency for acquisition of the synchronism.
申请公布号 JPS5573141(A) 申请公布日期 1980.06.02
申请号 JP19780146904 申请日期 1978.11.28
申请人 ANRITSU ELECTRIC CO LTD 发明人 OOSHIMA KOUICHI
分类号 H03L7/18;H03L7/16;H03L7/183 主分类号 H03L7/18
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