发明名称 |
SEMICONDUCTOR MEMORY CELL |
摘要 |
PURPOSE:To obtain a small-occupied area cell where a complicated sensor circuit is needless and operation can be performed in a low speed, by using two sets of transistors such as NPN transistors which form an FF-type memory cell and making current rise of them unbalanced. CONSTITUTION:A FF-type memory cell is formed by NPN transistors T1 and T2 which have emitters connected commonly and have collectors and bases connected to mutually. When line selection lines 1 and 5 are made high-level, transistor T6 which has the emitter connected commonly to transistors T1 and T2 is turned on and off according to turning-on and off of transistor T2, and storage contents dependent upon transistors T1 and T2 are read out by a low-speed operation without providing a sensor circuit through the collector on digit line D and having influence on the electrostatic capacity due to the high-level of lines 1 and 5. |
申请公布号 |
JPS5555496(A) |
申请公布日期 |
1980.04.23 |
申请号 |
JP19780128601 |
申请日期 |
1978.10.20 |
申请人 |
TOKYO SHIBAURA ELECTRIC CO |
发明人 |
AOKI KIYOSHI;ICHISE TAAKI |
分类号 |
G11C11/411;H01L21/8229;H01L27/02;H01L27/102;H03K19/091 |
主分类号 |
G11C11/411 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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