| 摘要 |
Decoder circuit arrangements for use with Josephson memory device arrays are disclosed. In one circuit of N stages, an input circuit consists of a Josephson junction and a shunting impedance connected across the junction by means of a matched transmission line. The transmission line has two output portions each of which controls the actuation or nonactuation of a pair of devices of circuits similar to the above-described circuit which are disposed in series in a pair of branches of a serially disposed superconducting loop of a first stage. Each branch has a serially disposed address gate to which true and complement address signals are applied. Each succeeding stage is similar to the first stage except that each branch of each succeeding stage contains twice as many circuits similar to the above-mentioned first stage circuit. In the last stage of the decoder, only one of a plurality of devices associated with the output of each of the circuits would be selected depending on which of the true or complement lines of each stage were actuated. These output devices could be array line drivers, for example. In another embodiment, in which all the address devices are disposed in series with the actuable device of an input stage, each of the address devices is shunted by a superconducting loop which, depending on a number of factors may or may not contain a serially disposed actuable device for resetting the address devices. The input stage consists of an actuable device and a shunting impedance connected across it by means of a transmission line which contains two output portions. Each of the output portions controls an actuable device disposed in series in each of the superconducting loops associated with the address devices of the first stage. Each of these actuable devices is shunted by an impedance using a transmission line which itself contains two output portions each of which is intended to control actuable devices disposed in series in the superconducting loops of the next stage.
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