发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To reduce the opportunity of production of a frequency difference and a phase difference before and after input interruption by devising the circuit such that an oscillating output keeping a phase in the normal state just before the interruption on the occurrence of a reference input signal. CONSTITUTION:A delay circuit 12 delays a phase control signal fed from a 1st frequency divider 3 by a multiple of (n) of a phase comparison period in a phase comparator circuit 6. A suppression circuit 14 delays an output signal of the delay circuit 12, that is, the phase control signal from the frequency divider 3 by a time nT to control the phase of a 3rd frequency divider 10. Then the suppression circuit 14 prevents a phase control signal from being given to the frequency divider 10 from the frequency divider 3 before any fluctuation incident within a time nT when a reference signal is interrupted gives any effect on the phase of the frequency division signal from the frequency divider 10. Moreover, a selection circuit 5 selects a frequency division output signal from the frequency divider 10 to be fed to the phase comparator circuit 6 and a control voltage is kept at the interruption of the input.
申请公布号 JPH0661850(A) 申请公布日期 1994.03.04
申请号 JP19920215877 申请日期 1992.08.13
申请人 NEC CORP 发明人 YUASA HIDEJI
分类号 H03L7/08;H03L7/14 主分类号 H03L7/08
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