| 摘要 |
<p>PURPOSE:To transfer data to a coprocessor only by one bus cycle by reading out the contents of a built-in cache memory or a main memory through a bus line at the time of a reading cycle. CONSTITUTION:At the time of transferring data to the coprocessor 200, bus interface parts 120 to 125 in a microprocessing unit (MPU) 100 instruct data reading from one of the built-in cache memory 130 and the main memory 300 to an external bus 400 in response to a memory address, a coprocessor data transfer instruction signal 117 and an external bus cycle starting signal 116 obtained from an execution part 100 and transfers the data read out to the bus 400 to the processor in one bus cycle. At the time of transferring data from the processor 200, data in the address position of the memory 130 corresponding to the memory address are purged. Data read out from the memory in the succeeding cycle are written in an address of the memory 130 corresponding to the memory address.</p> |
