| 摘要 |
PURPOSE:To enable to perform succeeding synchronous operation completely by correcting othe difference of delay and advance of generation of a receiving completion signal in the receiving portion by the use of a majority circuit. CONSTITUTION:Receiving completion detecting portion MPA (surrounded by a solid line) including majority circuit 40 is equipped in synchronous portion PC. In addition, the synchronous processing circuit of the triple logical device includes receivind portions R1 to R3, processing portions T1 to T3 and output portions S1 to S3. Moreover, MPA is constituted by FF1 to FF3 that store temporally receiving completion signals from each system according to each system, 2 input and gates G1P to G3P, 3 input ''or'' gate G5P (majority circuit 40 is constituted by combination of each gate), bynary counter CuP, decoder DECP that converts binary digit into decimal digit, 2 input and gate G4P, and inverter IV (counting circuit 50 is constituted by th units). Thus, when output q of circuit 40 is generated, counter 50 is advanced in every generation of clock pulse CP and, when the counting value of DECP reaches j, output rp is generated. |
