发明名称 |
Normalised capacitance measuring device - has stable oscillator feeding up=down counter circuit including memory system |
摘要 |
<p>A capacitance measurement circuit operates cyclically with a measuring phase and a normalising phase. It includes a high stability oscillator to which the unknown capacitor and a normalisation capacitor are connected. The evaluating circuit includes an up-and-down counter which triggers a second counter when a null state is reached. Coupled to the second counter is a memory, counter and indicator circuit which displays the normalised value of the unknown capacitance. A control circuit is coupled to the two counters. A clock pulse generator may supply different clock frequencies in the up and down counting modes.</p> |
申请公布号 |
FR2404229(A1) |
申请公布日期 |
1979.04.20 |
申请号 |
FR19770028758 |
申请日期 |
1977.09.23 |
申请人 |
TESTUT AEQUITAS |
发明人 |
GILBERT DAUGE ET JACQUES LANGLAIS;LANGLAIS JACQUES |
分类号 |
G01R19/252;G01R27/26;(IPC1-7):01R27/26;01L1/14 |
主分类号 |
G01R19/252 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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