发明名称 Dynamic merged load logic (MLL) and merged load memory (MLM)
摘要 MOS dynamic logic/shift registers employing as load elements either a parasitic bipolar transistor whose emitter is the drain of the MOS element, or the drain-substrate diode charged via bi-polar signals on the clock lines capacitively coupled to the drain. Uses for logic, memory, and imaging applications.
申请公布号 US4449224(A) 申请公布日期 1984.05.15
申请号 US19800220491 申请日期 1980.12.29
申请人 HARARI, ELIYAHOU 发明人 HARARI, ELIYAHOU
分类号 G11C19/28;H01L27/07;H01L27/105;H03K19/096;(IPC1-7):H01L27/04;G11C11/40;H01L29/78 主分类号 G11C19/28
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