| 摘要 |
<p>A terminal selector interface between a central processor and a plurality of terminals wherein information from a central processor is sent to all terminals simultaneously and the central processor "listens" to terminals individually. As each terminal is being addressed, the preceding addressed terminal is connected by means of a multiplexor switching means to the central processor. If the preceding terminal has information to transmit, it raises its carrier which aborts the partially sent succeeding address. The terminal selectors of the present invention may be connected in cascade to provide for additional terminals or to provide flexibility in system design.</p> |
