| 摘要 |
PURPOSE:To reduce the circuit scale of a frame synchronizing circuit by using a counter generating a pulse for each frame and using the counter for detecting a detection signal from an even frame synchronizing pattern detector and for detecting a detection signal from an even frame synchronizing pattern detector. CONSTITUTION:When a signal series including a frame synchronizing pattern is inputted to, an input point 1 and an even frame synchronizing pattern detec tion circuit 3-1 detects an even frame synchronizing pattern, the circuit outputs a high level pulse as a detection signal. The detection signal is inputted to a forward/backward protection circuit 6 via an AND circuit 4-1. A control circuit 6 switches an output to an AND circuit 4-3 from a low level to a high level and an output to an AND circuit 4-4 from a low level to a high level. An odd frame synchronizing pattern detection circuit 3-2 detects an odd frame synchronizing pattern at the same time and outputs the detection signal, the detection signal reaches the forward/backward protection circuit 6 through the AND circuit 4-2. |
