| 摘要 |
1496081 Charge-coupled devices HUGHES AIRCRAFT CO 24 Jan 1975 [25 Jan 1974] 3205/75 Heading H1K Means for injecting charge into a CCD while avoiding firstly the coupling back of voltage spikes from the clocked transfer electrodes into the injecting junction and secondly deleterious charge accumulation and bias voltage build up at the injecting junction during the OFF clock period on the first transfer electrode comprises an electrode structure 41 (Fig. 2) between the injecting junction 19 and the first clocked electrode 17, the electrode structure having applied thereto a steady bias voltage which induces a potential wall in the underlying semi-conductor 13. The wall serves as a reservoir of charge during the OFF clock period of the first clocked electrode 17, and isolates the injecting junction 19 against the coupling back of voltage spikes. The electrode structure 41 comprises a transfer portion 43 adjacent the injecting junction 19 and a storage portion 45 adjacent the first clocked electrode 17, the fixed potential well being deeper under the storage portion 45 than under the transfer portion 43. In the 2-phase arrangement of Fig. 2, in which each clocked electrode consists of electrically connected transfer portion 17a and storage portion 17b respectively on and embedded in SiO 2 layer 15, the two portions 43, 45 of the electrode structure 41 are similarly arranged. An output arrangement including two MOS transistors, only one of which is shown in Fig. 2 (51), is described in detail. The type of construction shown in Fig. 2 is applicable to an infra-red imaging array ineluding a plurality of InSb i-r detectors each of which feeds charge laterally into a corresponding stage of a CCD shift register via a fixed-voltage electrode structure such as 41. Each CCD stage consists of four pairs of clocked transfer and storage electrodes. The clocked transfer and storage electrodes which, in each CCD stage, are located nearest to the charge input arrangement from the detector are specially shaped to facilitate passage of injected charge into the main CCD stream (see Fig. 8, not shown). The clock frequency is synchronized to the rate at which an i-r image is stepped across the detectors, so that all the charges from an element of the image arrive at the final CCD stage simultaneously. Since this means that the charge temporarily accommodated in each successive CCD stage is larger than in its predecessor the channel width, as defined by highly-doped chargestopping strips running alongside opposed edges of the channel, is increased step-wise at each successive stage. Fig. 11 shows the application of the invention to a 3-phase shift register. Here all the electrodes lie in a common metallization level and the transfer and storage portions 145, 147 of the input electrode structure are electrically independent, being connected to different fixed voltages so that a deeper potential well is induced beneath the storage portion 147 than beneath the transfer portion 145.
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