METHODS AND APPARATUS FOR LOW-DENSITY PARITY CHECK DECODING USING HARDWARE-SHARING AND SERIAL SUM-PRODUCT ARCHITECTURE

摘要

A decoding method and a decoder are provided to decrease the number of calculation elements and to simplify a routing mechanism by using a hardware sharing scheme and a serial sum-product architecture. A size of a check node-bit node message from a check node decoder to a bit node is calculated based on a sum of converted sizes of bit-check node messages with respect to plural bit nodes which are connected to check nodes smaller than the converted size of the bit-check node message. A sign of the check-bit node message from the check node to the bit node is calculated by multiplying a product of signs of bit-check node messages from the bit nodes connected to the check node by a sign of the bit-check node message for the bit and check nodes.