| 摘要 |
<p>PURPOSE:To shorten the cell delay time by allowing cell accumulating means to execute a preliminarily determined number of write cycles to receive one cell from cell input means and allowing cell accumulating means to execute a preliminarily determined number of read cycles to transfer one cell to a switch means. CONSTITUTION:Cell accumulating means 5A and 5B execute the preliminarily determined number of write cycles to receive one cell 10 from cell input means 4A and 4B and execute the preliminarily determined number of read cycles to transfer one cell 10 to a switch means 8. Since cell accumulating means 5A and 5B execute the preliminarily determined number of write cycles to input a cell, the cell inputted from an input communication circuit can be taken as a candidate cell at the time of input of a part of a bit string constituting the cell to cell accumulating means 5A and 5B, and the cell delay time is shortened.</p> |
