| 摘要 |
<p>A timer circuit which includes an operational amplifier integrator circuit and a voltage comparator is disclosed. The timer is responsive to input pulses of positive and negative polarity, and is relatively insensitive to spurious discontinuities in the input signal. The timer period is based on the linear integration period of the integrator circuit, with the comparator circuit sensing the presence or absence or virtual ground at the inverting input of the integrator circuit. Embodiments as an equal operate and release timer and as a pulse correction timer circuit are disclosed.</p> |
