PROGRAMMABLE SIGNAL DISTRIBUTION SYSTEMS

摘要

1478685 Data transmission INTERNATIONAL BUSINESS MACHINES CORP 18 Sept 1974 [23 Nov 1973] 40626/74 Heading H4P A processing apparatus incorporates an arrangement to distribute timing i.e. clock signals, e.g. under programmable control, comprising an arrangement of cross point switches each coordinating with a memory cell which both determines and indicates the conductive state of associated switch each located at intersections of line sets, the cell being controlled to provide determined outputs for sets of inputs. Outputs may be complemented. Each switch may be considered as a pair of AND gates outputs from which provide an OR function; memory cells may be flip-flop circuits controlled by words in a shift register e.g. through a decoder. In the embodiment differential delays in transmission channels of differing length are compensated by a series of time displaced clock pulses provided and switched by a 12 x 14 matrix array each of cross point switches (12) (Fig. 3 not shown) having an associated memory cell (14). Each switch comprises AND gates (16, 18) to which clock inputs (Xa &c.) are applied. Array 10, Fig. 1 has columns (22, 26) to each of which 12 clock pair inputs are applied. Cells (14) receive output through word and bit decoders 28, 30 from shift register 32 into which address data is shifted by clock signals 1, 2, Output of 28 is 12 pairs of complimented signals XA, XA which are applied to array 10 to select appropriate cells. Similarly 30 provides outputs YA which select columns corresponding to the address. Complimented clock outputs a, a1 are taken from (Ya, Ya1) lines (22, 26). Suitable transistor circuits for various parts of the arrangement are given in Figs. 4, 6 and 7 (not shown).