发明名称 Digital transmission error detector - adds pulses in train and checks for data values in excess of given sum limit
摘要 <p>The error detector, for a digital transmission system, divides the binary pulse train such that the sum of the magnitudes of the pulses in each train forms a given limit or lies between two given limits. If the given limit is exceeded by certain pulse trains then an error is deemed to be present. The pulses are summed using a counter (UDC). The sync signal is used to delineate groups of pulses for counting -ie the sync signal is transmitted before each pulse train.</p>
申请公布号 CH586979(A5) 申请公布日期 1977.04.15
申请号 CH19740017252 申请日期 1974.12.24
申请人 VILLARS, CLAUDE 发明人
分类号 H04L1/24;(IPC1-7):04L1/00 主分类号 H04L1/24
代理机构 代理人
主权项
地址