| 摘要 |
A pair of binary counters controlled by identical clock pulses are synchronized by means of a plurality of comparison devices in the form of exclusive OR-circuits having their inputs excited each by a pair of signals derived from corresponding stages of said counters and having their outputs connected to the stage of the respective pair to be maintained in phase synchronism with the other stage of said pair. There is maintained as a result thereof an automatic synchronism between the instantaneous states of the counters after a relatively small number of counting operations following an initial out-of-step condition of the counters. In order to synchronize counters located at widely remote stations, such as a pair of counters serving as basic scrambling and unscrambling pulse generators at the transmitter and receiver of secrecy pulse signal transmission system, the instantaneous states of the transmitting counter are reproduced at the receiver by means of a shift register having an equal number of stages to the stages of said counter and being excited by a time-division control pulse series produced by scanning the stages of the transmitting counter at a frequency at least equal to the clock frequency times the number of counter stages, said control pulse series being transmitted from the transmitting to the receiving station through a suitable synchronizing signal channel. In this case, synchronization is effected between the receiving counter and said register replacing the transmitting counter. By the use of an adequate number of counter stages, repetitive patterns in the final scrambling pulse signal, facilitating deciphering by unauthorized persons, may be increased beyond the average message duration. |
