发明名称 CIRCUIT BOARD LAYERING TOOL
摘要 PURPOSE:To prevent relative offset with the layer material caused by measurement differences and enhance the alignment precision by specifying a hole diameter for the two metal boards layered on the top and bottom and the board layered in between during the layering formation process for at least 2 sets in cases when there are at least 4 sets of alignment cylindrical pins and metal board holes. CONSTITUTION:The diameter of the standard alignment holes 3, 6 on the upper/lower boards 1 and the intermediate board 2 is made slightly larger than the diameter of the standard pin 7 with this difference kept to a maximum of 0.1mm and to a size which achieves the desired alignment precision between the material layers in the layered circuit board 8 connected by the adhesion sheet 9. Further, the diameter of the escape holes 4, 5 found on the same upper/lower boards 1 and the intermediate board 2 are made substantially larger than the diameter of the pin 1 and even if there are shifts in the standard pin alignment caused by differences in the intermediate board 2 and the upper/lower boards 1 which arise because of temperature differences during the layer formation process, the hole diameter is set to a size so that the layered circuit board 8 is not prevented from coming into contact and shifting its position. As a result, disalignment of the intermediate board 2 caused by thermal expansion can be prevented.
申请公布号 JPH04206997(A) 申请公布日期 1992.07.28
申请号 JP19900339357 申请日期 1990.11.30
申请人 HITACHI CHEM CO LTD 发明人 IKUI EISAKU
分类号 B32B37/10;B29C43/20;B29L31/34;H05K3/46 主分类号 B32B37/10
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