发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To suppress variation of shift quantity of timing of a control signal to the minimum by generating a read-out control signal or a write-in control signal of which timing is shifted by a prescribed quantity for a switch control signal using a prescribed delay element. SOLUTION: A first timing control circuit 49a generates a read-out control signal SEBZ by using a delay circuit 51 being a delay element being equivalent to a load of a prescribed wiring, a logic circuit 55, a delay circuit 53 being a delay element being equivalent to an average value of a load of the prescribed wiring, a logic circuit 57, and a delay gate 59. Therefore, a generated read-out control signal SEBZ is activated by being delayed by a delay time of the delay gate 59 for an average value of activating timing of a column selecting signal. As a delay time of the delay circuit 53 is an average value of a load of a wiring of a column decoding signal, shift quantity among a column selecting signal, a read-out control signal SEBZ, and write-in control signal is stored always in the prescribed range.
申请公布号 JP2000357391(A) 申请公布日期 2000.12.26
申请号 JP19990167001 申请日期 1999.06.14
申请人 FUJITSU LTD 发明人 SHINOZAKI NAOHARU
分类号 G11C11/407;G11C7/20;G11C7/22;G11C11/401;G11C11/409;G11C29/02;G11C29/12;G11C29/14;G11C29/50;(IPC1-7):G11C11/407;G11C29/00 主分类号 G11C11/407
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