发明名称 |
System and method for reducing power consumption by estimating engine load and reducing engine clock speed |
摘要 |
A computer system has at least one processor and at least one queue for storing instructions for execution by the processor. The processor is capable of being clocked at a plurality of rates. A number of instructions in the queue is measured. The optimum clock rate is selected based on in part the determined number of queued instructions.
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申请公布号 |
US2005044435(A1) |
申请公布日期 |
2005.02.24 |
申请号 |
US20040813595 |
申请日期 |
2004.03.30 |
申请人 |
ATI INTERNATIONAL, SRL |
发明人 |
ZDRAVKOVIC ANDREJ |
分类号 |
G06F1/32;(IPC1-7):G06F1/32 |
主分类号 |
G06F1/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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