| 摘要 |
A low-profile, folded-plate, dynamic random access memory (DRAM) cell capacitor which can be fabicated with only two photoresist masks using equipment and processes identical to those used for the fabrication of DRAM cells having planar capacitors. The n+ silicon substrate, which is an extension of the cell's field-effect transistor drain, functions as the lower half of the capacitor's storage-node plate. The capacitor's field plate is comprised of a doped polycrystalline silicon-2 (poly-2) layer. The field plate is insulated on its lower surface from the n+ silicon substrate by a first dielectric layer of silicon nitride; it is insulated on its edges with a silicon oxide dielectric and on its upper surface with a second dielectric layer of silicon nitride from the upper half of the storage-node plate, which is comprised of a sandwich of n-type poly-3 and poly-4 layers. The upper half of the storage-node plate is tied to the n+ silicon substrate with a buried contact which is an extension of the poly-4-layer. The folded-plate capacitor, compared with a planar capacitor occupying comparable cell surface area, has essentially double the capacitance and greater resistance to alpha-particle-generated soft errors.
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