发明名称 Multilayer circuit structure having projecting via lead
摘要 A multilayer structure is fabricated by forming a conductive layer on an insulative substrate. A first conductive pattern is formed on the first conductive layer and a resist layer having a via hole therethrough is formed on the first pattern. A via lead is formed in the via hole by electrically plating a metal therein utilizing the first layer as a lead for the plating process. The resist and the exposed part of the first layer are removed and a polyimide layer having a thermal expansion coefficient that is equal to that of the via lead is formed over the substrate. The surface of the polyimide layer is etched until the via lead top segment protrudes to a predetermined height above the surface of the etched polyimide layer. A second pattern is formed on the polyimide layer and the exposed lead segment by a plating process.
申请公布号 US5562970(A) 申请公布日期 1996.10.08
申请号 US19950481830 申请日期 1995.06.07
申请人 FUJITSU LTD. 发明人 SATOH, KAZUAKI
分类号 H01L21/48;H05K3/00;H05K3/10;H05K3/24;H05K3/46;(IPC1-7):B32B9/00 主分类号 H01L21/48
代理机构 代理人
主权项
地址