| 摘要 |
PURPOSE:To save a high-speed multiplier required for chrominance signal processing by inputting an output signal of a multiplier and adding/subtracting the said signal and the resulting signal applied with a prescribed time delay to the said signal thereby extracting the result in a prescribed timing. CONSTITUTION:A chrominance signal C is inputted to a signal conversion circuit 401, where the signal is converted into a chrominance signal C10. Further, a data selecting circuit 500 gives a multiplier and a multiplicand to a multiplier 403. A multiplexer 402 processes selectively an ACC signal A0 and the C10, its output signal C11 is inputted to the multiplier 403 and multiplied with an output signal K10 from a multiplexer 427. An output signal C12 of the multiplier 403 is subjected to ACC control, color saturation adjustment and hue adjustment, matrix arithmetic is given at a delay circuit 430, an adder 431, and registers 432-434 and the signal is separated into R-Y, G-Y and B-Y signals.
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